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november 2004 copyright ? alliance semiconductor. all rights reserved. ? as7c33512pfd18a 3.3v 512k 18 pipeline burst synchronous sram 12/1/04; v.1.3 alliance semiconductor 1 of 20 features ? organization: 524,288 words 18 bits ? fast clock speeds to 166 mhz ? fast clock to data access: 3.5/4.0 ns ?fast oe access time: 3.5/4.0 ns ? fully synchronous register-to-register operation ? dual-cycle deselect ? asynchronous output enable control ? individual byte write and global write ? available in 100-pin tqfp package ? linear or interleaved burst control ? snooze mode for reduced power-standby ? common data inputs and data outputs ? byte write enables ? multiple chip enables for easy expansion ? 3.3v core power supply ? 2.5v or 3.3v i/o operation with separate v ddq selection guide ?166 ?133 units minimum cycle time 6 7.5 ns maximum clock frequency 166 133 mhz maximum clock access time 3.5 4 ns maximum operating current 475 425 ma maximum standby current 130 100 ma maximum cmos standby current (dc) 30 30 ma logic block diagram burst logic adv adsc adsp clk lbo clk clr cs 19 17 19 a[18:0] 19 address d q cs clk register 512k 18 memory array 18 18 dqb clk dq byte write registers dqa clk dq byte write registers enable clk dq register enable clk dq delay register ce output registers input registers power down 2 ce0 ce1 ce2 bw b bw a oe zz oe clk clk bwe gwe 18 dq[a,b]
? as7c33512pfd18a 12/1/04; v.1.3 alliance semiconductor 2 of 20 8 mb synchronous sram products list 1,2 1 core power supply: vdd = 3.3v + 0.165v 2 i/o supply voltage: vddq = 3.3v + 0.165v for 3.3v i/o vddq = 2.5v + 0.125v for 2.5v i/o pl-scd : pipelined burst synchronous sram - single cycle deselect pl-dcd : pipelined burst synchronous sram - double cycle deselect ft : flow-through burst synchronous sram ntd 1 -pl : pipelined burst synchronous sram with ntd tm ntd-ft : flow-through burst s ynchronous sram with ntd tm org part number mode speed 512kx18 as7c33512pfs18a pl-scd 166/133 mhz 256kx32 as7c33256pfs32a pl-scd 166/133 mhz 256kx36 as7c33256pfs36a pl-scd 166/133 mhz 512kx18 as7c33512pfd18a pl-dcd 166/133 mhz 256kx32 as7c33 256 pfd32a pl-dcd 166/133 mhz 256kx36 as7c33 256 pfd36a pl-dcd 166/133 mhz 512kx18 as7c33512ft18a ft 7.5/8.5/10 ns 256kx32 as7c33 256 ft32a ft 7.5/8.5/10 ns 256kx36 as7c33 256 ft36a ft 7.5/8.5/10 ns 512kx18 as7c33512ntd18a ntd-pl 166/133 mhz 256kx32 as7c33 256 ntd32a ntd-pl 166/133 mhz 256kx36 as7c33 256 ntd36a ntd-pl 166/133 mhz 512kx18 as7c33512ntf18a ntd-ft 7.5/8.5/10 ns 256kx32 as7c33 256 ntf32a ntd-ft 7.5/8.5/10 ns 256kx36 as7c33 256 ntf36a ntd-ft 7.5/8.5/10 ns 1. ntd: no turnaround delay. ntd tm is a trademark of alliance semiconduct or corporation. all trad emarks mentioned in this document are the prop- erty of their respective owners.
? as7c33512pfd18a 12/1/04; v.1.3 alliance semiconductor 3 of 20 pin arrangement lbo a a a a a1 a0 nc nc v ss v dd nc a a a a a a a 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a ce0 ce1 nc nc bwb bwa ce2 v dd v ss clk gwe bwe oe adsc adsp adv a a a nc nc nc v ddq v ssq nc nc dqb0 dqb1 v ssq v ddq dqb2 dqb3 nc v dd nc v ss dqb4 dqb5 v ddq v ssq dqb6 dqb7 dqpb nc v ssq v ddq nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 a nc nc v ddq v ssq nc dqpa dqa7 dqa6 v ssq v ddq dqa5 dqa4 vss zz dqa3 dqa2 v ddq v ssq dqa1 dqa0 nc nc v ssq v ddq nc nc nc nc v dd tqfp 14 20mm
? as7c33512pfd18a 12/1/04; v.1.3 alliance semiconductor 4 of 20 functional description the as7c33512pfd18a is a high performance cmos 8-mbit synchronous static random acce ss memory (sram) devices organized as 524,288 words 18 bits and incorporate a pipeli ne for highest frequency on any given technology. fast cycle times of 6/7.5 ns with clock access times (t cd ) of 3.5/4.0 ns enable 166 and 133 mhz bus frequencies. three chip enable inputs permit easy memory expansion. burst operation is initiated in one of two wa ys: the controller address strobe (adsc ), or the processor address strobe (adsp ). the burst advance pin (adv ) allows subsequent interna lly generated burst addresses. read cycles are initiated with adsp (regardless of we and adsc ) using the new external address clocke d into the on-chip address register. when adsp is sampled low, the chip enables are sampled active, and the output buffer is enabled with oe . in a read operation the data accessed by the current addre ss, registered in the address regi sters by the positive edge of clk, are carried to the data-out r egisters and driven on the output pins on the next positive edge of clk. adv is ignored on the clock edge that samples adsp asserted but is sampled on all subsequent cl ock edges. address is increm ented internally for the next access of the burst when adv is sampled low and both address strobes are high. burst mode is selectable with the lbo input. with lbo unconnected or driven high, burst operations use a pentium ?1 count sequence. with lbo driven low the device uses a linear count sequence suitable for powerpc ? and many other applications. write cycles are performed by disa bling the output buffers with oe and asserting a write comma nd. a global write enable gwe writes all 18 bits regardless of the st ate of individual bw[a:b] inputs. alternately, when gwe is high, one or more byte s may be written by asserting bwe and the appropriate individual byte bwn signal(s). bwn is ignored on the clock edge that samples adsp low, but is sampled on all subsequent cloc k edges. output buffers are disabled when bwn is sampled low (regardless of oe ). data is clocked into the data input register when bwn is sampled low. address is incremented internally to the next burst address if bwn and adv are sampled low. this device operates in double- cycle deselect feature during read cycles. read or write cycles may also be initiated with adsc instead of adsp . the differences between cycles initiated with adsc and adsp are as follows: ? adsp must be sampled high when adsc is sampled low to initiate a cycle with adsc . ? we signals are sampled on the clock edge that samples adsc low (and adsp high). ? master chip select ce0 blocks adsp , but not adsc . the as7c33512pfd18a operate from a 3. 3v supply. i/os use a separate power supply that can operate at 2.5v or 3.3v. these device s are available in a 100-pin 1420 mm tqfp packaging. . * guaranteed not tested 1. powerpc ? is a trademark inte rnational business machines corporation capacitance parameter symbol test conditions max unit input capacitance c in * v in = 0v 5 pf i/o capacitance c i/o * v in = v out = 0v 7 pf tqfp thermal resistance description conditions symbol typical units thermal resistance (junction to ambient) 1 1 this parameter is sampled. test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51 1?layer ja 40 c/w 4?layer ja 22 c/w thermal resistance (junction to top of case) 1 jc 8 c/w
? as7c33512pfd18a 12/1/04; v.1.3 alliance semiconductor 5 of 20 snooze mode snooze mode is a low current , power-down mode in which the device is deselected and current is reduced to i sb2 . the duration of snooze mode is dictated by the lengt h of time the zz is in a high state. the zz pin is an asynchronous, active high input that causes the device to enter snooze mode. when the zz pin becomes a logic high, i sb2 is guaranteed after the time t zzi is met. after entering snoo ze mode, all inputs except zz is disabled and all outputs go to high-z. any operation pending when entering snooze mode is not guaranteed to successfully com plete. therefore, snooze mode (read or write) mu st not be initiated until valid pending opera tions are completed. similarly, when exit ing snooze mode during t pus , only a deselect or read cycl e should be given while the sram is transitioning out of snooze mode. signal descriptions signal i/o properties description clk i clock clock. all inputs except oe , zz, lbo are synchronous to this clock. a,a0,a1 i sync address. sampled when all chip enables are active and adsc or adsp are asserted. dq[a,b] i/o sync data. driven as outpu t when the chip is enabled and oe is active. ce0 isync master chip enable. sampled on clock edges when adsp or adsc is active. when ce0 is inactive, adsp is blocked. refer to the synchronous truth table for more information. ce1, ce2 isync synchronous chip enables. active high and active low, respectively. sampled on clock edges when adsc is active or when ce0 and adsp are active. adsp i sync address strobe (processor). asserted low to load a new address or to enter standby mode. adsc i sync address strobe (controller). asserted low to load a new address or to enter standby mode. adv i sync burst advance. asserted low to continue burst read/write. gwe isync global write enable. asserted low to write all 18 bits. when high, bwe and bw[a,b] control write enable. bwe i sync byte write enable. asserted low with gwe = high to enable effect of bw[a,b] inputs. bw[a,b] isync write enables. used to cont rol write of individual bytes when gwe = high and bwe = low. if any of bw[a,b] is active with gwe = high and bwe = low the cycle is a write cycle. if all bw[a,b] are inactive, the cycle is a read cycle. oe iasync asynchronous output enable. i/ o pins are driven when oe is active and the chip is in read mode. lbo istatic selects burst mode. when tied to v dd or left floating, device follows interleaved burst order. when driven low, device follows linear burst order. this signal is internally pulled high. zz i async snooze. places device in low power mode; data is retain ed. connect to gnd if unused. nc - - no connect
? as7c33512pfd18a 12/1/04; v.1.3 alliance semiconductor 6 of 20 write enable truth table (per byte) key: x = don?t care, l = low, h = high, n = a, b; bwe , bwn = internal write signal. asynchronous truth table burst sequence table function gwe bwe bwa bwb write all bytes lxxx hlll write byte a h l l h write byte b h l h l read hhxx hlhh operation zz oe i/o status snooze mode h x high-z read l l dout lhhigh-z write l x din, high-z deselected l x high-z interleaved burst address (lbo = 1) linear burst address (lbo = 0) a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 starting address 0 0 0 1 1 0 1 1 starting address 0 0 0 1 1 0 1 1 first increment 0 1 0 0 1 1 1 0 first increment 0 1 1 0 1 1 0 0 second increment 1 0 1 1 0 0 0 1 s econd increment 1 0 1 1 0 0 0 1 third increment 1 1 1 0 0 1 0 0 third increment 1 1 1 0 0 1 1 0
? as7c33512pfd18a 12/1/04; v.1.3 alliance semiconductor 7 of 20 synchronous truth table [4] ce0 1 1 x = don?t care, l = low, h = high ce1 ce2 adsp adsc adv write [2] 2 for write , l means any one or more byte write enable signals (bwa or bwb ) and bwe are low or gwe is low. write = high for all bwx , bwe , gwe high. see "write enable truth table (per byte)," on page 6 for more information. oe address accessed clk operation dq hxxxlx x x na l to h deselecthi ? z l l x l x x x x na l to h deselect hi ? z l l x h l x x x na l to h deselect hi ? z l x h l x x x x na l to h deselect hi ? z l x h h l x x x na l to h deselect hi ? z l h l l x x x l external l to h begin read q l h l l x x x h external l to h begin read hi ? z l h l h l x h l external l to h begin read q l h l h l x h h external l to h begin read hi ? z xxxhhl h l next l to hcontinue readq xxxhhl h h next l to hcontinue readhi ? z xxxhhh h l current l to hsuspend readq xxxhhh h h current l to hsuspend readhi ? z hxxxhl h l next l to hcontinue readq hxxxhl h h next l to hcontinue readhi ? z hxxxhh h l current l to hsuspend readq hxxxhh h h current l to hsuspend readhi ? z l h l h l x l x external l to h begin write d 3 3 for write operation following a read, oe must be high before the inpu t data set up time and held high throughout the input hold time 4 zz pin is always low. xxxhhl l x next l to hcontinue writed hxxxhl l x next l to hcontinue writed xxxhhh l x current l to hsuspend writed hxxxhh l x current l to hsuspend writed
? as7c33512pfd18a 12/1/04; v.1.3 alliance semiconductor 8 of 20 recommended operating conditions at 3.3v i/o recommended operating conditions at 2.5v i/o absolute maximum ratings 1 1 stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outsid e those indicated in the operatio nal sections of this specificat ion is not implied. exposure to absolute maximum rating conditions may affect reliability. parameter symbol min max unit power supply voltage relative to gnd v dd , v ddq ?0.5 +4.6 v input voltage relative to gnd (input pins) v in ?0.5 v dd + 0.5 v input voltage relative to gnd (i/o pins) v in ?0.5 v ddq + 0.5 v power dissipation p d ?1.8w dc output current i out ?50ma storage temperature (plastic) t stg ?65 +150 c temperature under bias t bias ?65 +135 c parameter symbol min nominal max unit supply voltage for inputs v dd 3.135 3.3 3.465 v supply voltage for i/o v ddq 3.135 3.3 3.465 v ground supply vss 0 0 0 v parameter symbol min nominal max unit supply voltage for inputs v dd 3.135 3.3 3.465 v supply voltage for i/o v ddq 2.375 2.5 2.625 v ground supply vss 0 0 0 v
? as7c33512pfd18a 12/1/04; v.1.3 alliance semiconductor 9 of 20 dc electrical characteristics for 3.3v i/o operation dc electrical characteristics for 2.5v i/o operation * v ih max < vdd +1.5v for pulse width less than 0.2 x t cyc ** v il min = -1.5 for pulse wi dth less than 0.2 x t cyc i dd operating conditions and maximum limits parameter sym conditions min max unit input leakage current 1 1 lbo , and zz pins and the have an internal pull-up or pull-down, and input leakage = 10 a. |i li |v dd = max, 0v < v in < v dd -2 2 a output leakage current |i lo |oe v ih , v dd = max, 0v < v out < v ddq -2 2 a input high (logic 1) voltage v ih address and control pins 2 * v dd +0.3 v i/o pins 2 * v ddq +0.3 input low (logic 0) voltage v il address and control pins -0.3 ** 0.8 v i/o pins -0.5 ** 0.8 output high voltage v oh i oh = ?4 ma, v ddq = 3.135v 2.4 ? v output low voltage v ol i ol = 8 ma, v ddq = 3.465v ? 0.4 v parameter sym conditions min max unit input leakage current |i li |v dd = max, 0v < v in < v dd -2 2 a output leakage current |i lo |oe v ih , v dd = max, 0v < v out < v ddq -2 2 a input high (logic 1) voltage v ih address and control pins 1.7 * v dd +0.3 v i/o pins 1.7 * v ddq +0.3 v input low (logic 0) voltage v il address and control pins -0.3 ** 0.7 v i/o pins -0.3 ** 0.7 v output high voltage v oh i oh = ?4 ma, v ddq = 2.375v 1.7 ? v output low voltage v ol i ol = 8 ma, v ddq = 2.625v ? 0.7 v parameter sym conditions -166 -133 unit operating power supply current 1 1 i cc given with no output loading. i cc increases with faster cycle times and greater output loading. i cc ce0 < v il , ce1 > v ih , ce2 < v il , f = f max , i out = 0 ma, zz < v il 475 425 ma all v in 0.2v or > v dd ? 0.2v, deselected, f = f max , zz < v il standby power supply current i sb deselected, f = 0, zz < 0.2v, all v in 0.2v or v dd ? 0.2v 130 100 ma i sb1 deselected, f = f max , zz v dd ? 0.2v, all v in v il or v ih 30 30 i sb2 ce0 < v il , ce1 > v ih , ce2 < v il , f = f max , i out = 0 ma, zz < v il 30 30
? as7c33512pfd18a 12/1/04; v.1.3 alliance semiconductor 10 of 20 timing characteristics for 3.3 v i/o operation parameter symbol ?166 ?133 unit notes 1 min max min max clock frequency f max ?166?133mhz cycle time t cyc 6 ? 7.5 ? ns clock access time t cd -3.5-4.0ns output enable low to data valid t oe ?3.5?4.0ns clock high to output low z t lzc 0 ? 0 ? ns 2,3,4 data output invalid from clock high t oh 1.5 ? 1.5 ? ns 2 output enable low to output low z t lzoe 0 ? 0 ? ns 2,3,4 output enable high to output high z t hzoe ?3.5?4.0ns 2,3,4 clock high to output high z t hzc ?3.5?4.0ns 2,3,4 output enable high to invalid output t ohoe 0?0?ns clock high pulse width t ch 2.4 ? 2.5 ? ns 5 clock low pulse width t cl 2.3 ? 2.5 ? ns 5 address setup to clock high t as 1.5 ? 1.5 ? ns 6 data setup to clock high t ds 1.5 ? 1.5 ? ns 6 write setup to clock high t ws 1.5 ? 1.5 ? ns 6,7 chip select setup to clock high t css 1.5 ? 1.5 ? ns 6,8 address hold from clock high t ah 0.5 ? 0.5 ? ns 6 data hold from clock high t dh 0.5 ? 0.5 ? ns 6 write hold from clock high t wh 0.5 ? 0.5 ? ns 6,7 chip select hold from clock high t csh 0.5 ? 0.5 ? ns 6,8 adv setup to clock high t advs 1.5 ? 1.5 ? ns 6 adsp setup to clock high t adsps 1.5 ? 1.5 ? ns 6 adsc setup to clock high t adscs 1.5 ? 1.5 ? ns 6 adv hold from clock high t advh 0.5 ? 0.5 ? ns 6 adsp hold from clock high t adsph 0.5 ? 0.5 ? ns 6 adsc hold from clock high t adsch 0.5 ? 0.5 ? ns 6 1 see ?notes? on page 17
? as7c33512pfd18a 12/1/04; v.1.3 alliance semiconductor 11 of 20 snooze mode electrical characteristics timing characteristics for 2.5v i/o operation parameter symbol ?166 ?133 unit notes 1 min max min max clock frequency f max ? 166 ? 133 mhz cycle time t cyc 6 ? 7.5 ? ns clock access time t cd -4.0-4.5ns output enable low to data valid t oe ?3.5?4.0ns clock high to output low z t lzc 0 ? 0 ? ns 2,3,4 data output invalid from clock high t oh 1.5?1.5? ns 2 output enable low to output low z t lzoe 0 ? 0 ? ns 2,3,4 output enable high to output high z t hzoe ? 3.5 ? 4.0 ns 2,3,4 clock high to output high z t hzc ? 3.5 ? 4.0 ns 2,3,4 output enable high to invalid output t ohoe 0?0?ns clock high pulse width t ch 2.4?2.5? ns 5 clock low pulse width t cl 2.3?2.5? ns 5 address setup to clock high t as 1.7?1.7? ns 6 data setup to clock high t ds 1.7?1.7? ns 6 write setup to clock high t ws 1.7 ? 1.7 ? ns 6,7 chip select setup to clock high t css 1.7 ? 1.7 ? ns 6,8 address hold from clock high t ah 0.7?0.7? ns 6 data hold from clock high t dh 0.7?0.7? ns 6 write hold from clock high t wh 0.7 ? 0.7 ? ns 6,7 chip select hold from clock high t csh 0.7 ? 0.7 ? ns 6,8 adv setup to clock high t advs 1.7?1.7? ns 6 adsp setup to clock high t adsps 1.7?1.7? ns 6 adsc setup to clock high t adscs 1.7?1.7? ns 6 adv hold from clock high t advh 0.7?0.7? ns 6 adsp hold from clock high t adsph 0.7?0.7? ns 6 adsc hold from clock high t adsch 0.7?0.7? ns 6 1 see notes on page 17. description conditions symbol min max units current during snooze mode zz > v ih i sb2 30 ma zz active to input ignored t pds 2cycle zz inactive to input sampled t pus 2cycle zz active to snooze current t zzi 2cycle zz inactive to exit snooze current t rzzi 0 . .
? as7c33512pfd18a 12/1/04; v.1.3 alliance semiconductor 12 of 20 key to switching waveforms timing waveform of read cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. bw[a:d] is don?t care. *outputs are disabled within two clk cycles after dsel command don?t care falling input rising input undefined ce1 t cyc t ch t cl t adsps t adsph t as t ah t ws t advs t oh clk adsp adsc address gwe , bwe ce0 , ce2 adv oe dout t css t hzc t cd t wh t advh t hzoe t adscs t adsch load new address adv inserts wait states q(a2y10) q(a2y11) q(a3) q(a2) q(a2y01) q(a3y01) q(a3y10) q(a1) a2 a1 a3 t oe t lzoe t csh read q(a1) suspend read q(a1) read q(a2) burst read q(a 2y01 ) read q(a3) dsel * burst read q(a 2y10 ) suspend read q(a 2y10 ) burst read q(a 2y11 ) burst read q(a 3y01 ) burst read q(a 3y10 ) burst read q(a 3y11 )
? as7c33512pfd18a 12/1/04; v.1.3 alliance semiconductor 13 of 20 timing waveform of write cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. t cyc t cl t adsps t adsph t adscs t adsch t as t ah t ws t wh t css t advs t ds t dh clk adsp adsc address bwe ce0 , ce2 adv oe din t csh t advh d(a2y01) d(a2y10) d(a3) d(a2) d(a2y01) d(a3y01) d(a3y10) d(a1) d(a2y11) adv suspends burst adsc loads new address a1 a2 a3 t ch ce1 bw[a:b] read q(a1) sus- pend write d(a1) read q(a2) suspend write d(a 2 ) adv burst write d(a 2y01 ) suspend write d(a 2y01 ) adv burst write d(a 2y10 ) write d(a 3 ) burst write d(a 3y01 ) adv burst write d(a 2y11 ) adv burst write d(a 3y10 )
? as7c33512pfd18a 12/1/04; v.1.3 alliance semiconductor 14 of 20 timing waveform of read/write cycle (adsp controlled; adsc high) note: y = xor when lbo = high/no connect; y = add when lbo = low. t ch t cyc t cl t adsps t adsph t as t ah t ws t wh t advs t ds t dh t oh clk adsp address gwe ce0 , ce2 adv oe din dout t cd t advh t lzoe t oe t lzc q(a1) q(a3y01) d(a2) q(a3) q(a3y10) q(a3y11) a1 a2 a3 ce1 t hzoe dsel suspend read q(a1) read q(a1) suspend write d(a 2 ) adv burst read q(a 3y01 ) adv burst read q(a 3y10 ) adv burst read q(a 3y11 ) read q(a2) read q(a3)
? as7c33512pfd18a 12/1/04; v.1.3 alliance semiconductor 15 of 20 timing waveform of read/write cycle(adsc controlled, adsp = high) t cyc t ch t cl t adsch clk adsc address a2 a1 t adscs a3 a4 a6 a5 a7 a8 a9 t ah t as gwe t wh t ws t csh ce0 ,ce2 t css adv t lzoe t oe t hzoe q(a1) q(a2) q(a3) q(a4) q(a8) q(a9) t lzoe t oh d(a6) d(a7) d(a5) t ds t dh oe dout din read q(a1) read q(a2) read q(a3) read q(a4) write d(a5) write d(a6) write d(a7) read q(a8) read q(a9) ce1
? as7c33512pfd18a 12/1/04; v.1.3 alliance semiconductor 16 of 20 timing waveform of power down cycle t cyc t ch t cl t adsps clk adsp address a1 t adsps a2 gwe t wh t ws t csh ce0 ,ce2 t css adv t lzoe t oe t hzoe q(a1) d(a2( y 01)) d(a2) oe dout din adsc t hzc t pds zz setup cycle t pus zz recovery cycle n ormal operation mode ce1 zz read q(a1) s uspend read q(a1) c on - tinue write d(a2 y 01) s uspend write d(a2) read q(a2) sleep i sb2 state t zzi t rzzi i supply
? as7c33512pfd18a 12/1/04; v.1.3 alliance semiconductor 17 of 20 ac test conditions z 0 = 50 ? d out 50 ? figure b: output load (a) 30 pf* figure a: input waveform 10% 90% gnd 90% 10% +3.0v ? output load: see figure b, except for t lzc , t lzoe , t hzoe , t hzc , see figure c. ? input pulse level: gnd to 3v. see figure a. ? input rise and fall time (measured at 0.3v an d 2.7v): 2 ns. see figure a. ? input and output timing reference levels: 1.5v. v l = 1.5v for 3.3v i/o; = v ddq /2 for 2.5v i/o n otes: 1) for test cond itions, see ?ac test conditions?, figures a, b, c 2) this parameter measured with output load condition in figure c. 3) this parameter is sampled, but not 100% tested. 4) t hzoe is less than t lzoe and t hzc is less than t lzc at any given temperature and voltage. 5) t ch measured high above v ih and t cl measured as low below v il 6) this is a synchronous device. all addresses must meet the sp ecified setup and hold times for all rising edges of clk. all ot her synchronous inputs mus t meet the setup and hold times with stable logic levels for all risi ng edges of clk when chip is enabled. 7) write refers to gwe , bwe , bw[a,b] . 8) chip select refers to ce0 , ce1 , ce2 . 353 ? / 1538? 5 pf* 319 ? / 1667? d out gnd figure c: output load (b) *including scope and jig capacitanc e thevenin equivalent: +3.3v for 3.3v i/o; /+2.5v for 2.5v i/o
? as7c33512pfd18a 12/1/04; v.1.3 alliance semiconductor 18 of 20 package dimensions 100-pin quad flat pack (tqfp) a1 a2 l1 l c he e hd d b e tqfp min max a1 0.05 0.15 a2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 d 13.90 14.10 e 19.90 20.10 e 0.65 nominal hd 15.90 16.10 he 21.90 22.10 l 0.45 0.75 l1 1.00 nominal 0 7 dimensions in millimeters
? as7c33512pfd18a 12/1/04; v.1.3 alliance semiconductor 19 of 20 note: add suffix ?n? with the above pa rt number for lead free parts (ex. as 7c33512pfd18a -166tqcn) 1. alliance semiconductor sram prefix 2. operating voltage: 33=3.3v 3. organization: 512 = 512 k 4. pipelined mode 5. deselect : d=double cycle deselect 6. organization: 18=x18 7. production version: a= first production version 8. clock speed (mhz) 9. package type: tq=tqfp 10. operating temperature: c=commercial ( 0 c to 70 c); i=industrial ( -40 c to 85 c) 11. n = lead free part ordering information package ?166 mhz ?133 mhz tqfp x18 as7c33512pfd18a-166tqc as7c33512pfd18a-133tqc tqfp x18 as7c33512pfd18a-166tqi as7c33512pfd18a-133tqi part numbering guide as7c 33 512 pf d 18 a ?xxx tq c/i x 1 23 4 5 6789 10 11
alliance semiconductor corporation 2575, augustine drive, santa clara, ca 95054 tel: 408 - 855 - 4900 fax: 408 - 855 - 4999 www.alsc.com copyright ? alliance semiconductor all rights reserved part number: as7c33512pfd18a document version: v.1.3 ? copyright 2003 alliance semiconductor corporation. all rights re served. our three-point logo, our name and intelliwatt are tr ademarks or registered trademarks of alli- ance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to mak e changes to this docu ment and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contai ned herein represents al liance's best data and/ or estimates at the time of issuance. allian ce reserves the right to change or correct this data at any time, without notice. i f the product described he rein is under develop- ment, significant changes to these specifications are possible. the information in this product data sheet is intended to be ge neral descriptive information for potential cus- tomers and users, and is not in tended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance d oes not assume any responsibility or liability arising out of the application or use of any product described herein, a nd disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellec tual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusivel y according to alliance's terms and condi- tions of sale. the purchase of products from alliance does not convey a license under a ny patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third part ies. alliance does not authorize its products for use as critical components in life-s upporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alli ance products in such life-sup porting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. ? as7c33512pfd18a ?

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